The present invention relates to a semiconductor integrated circuit device and more particularly to a mode switching technique about trimming or estimation of an internal circuit included in the above device.
A semiconductor integrated circuit device requires trimming in a delay step for adjusting voltage level of the internal power created by an internal step-down transformer and various timing. The trimming is performed by fixing logic with a fuse circuit and an estimation pad in a step of wafer probing.
AC characteristics such as setup/hold characteristic and clock access are defined as a spec in the input and output terminals of a semiconductor integrated circuit device such as a microcomputer and a memory. An electronic device having a lot of semiconductor integrated circuit devices on a print board requires timing adjustment of signal input and output, owing to unevenness in manufacture of semiconductor elements and delay of a signal according to the pattern writing length or the like. As a technique for flexibly adjusting the timing of a signal by freely changing the AC characteristics, there is known a technique enabling the timing adjustment of signal input and output by providing delaying means for freely delaying a clock signal to be supplied to a latch provided in the I/O terminal, according to a control signal and a boundary scan circuit for setting a delay of this delaying means, for example, as described in Japanese Patent Laid-Open No. 289322/1999.
In the trimming using a fuse, however, it is impossible to trim a semiconductor again after breaking the fuse or sealing the semiconductor chip into a package. When a fuse is broken in one trimming, the fuse cannot be used any more for another trimming. Accordingly, fault analysis becomes difficult in a sample shipped to a customer, in the case of using a fuse. Further, the same sample may be desired to be estimated again in another trimming spec in some cases, but this is impossible and in order to cope with the above case, every fuse is broken so as to prepare various trimming specs for every sample.
Further, according to the technique described in Japanese Patent Laid-Open No. 289322/1999, timing of signal input and output can be adjusted even after sealing a semiconductor chip into a package, by using a boundary scan circuit. However, it is not only the AC characteristics such as setup/hold characteristic and clock access that require the trimming and estimation in a semiconductor integrated circuit device. For example, trimming is required for voltage level of an internal power that is a dynamic operation of an internal circuit and pulse width of a word line selecting signal and a column selecting signal for selecting a memory cell. According to the technique described in Japanese Patent Laid-Open No. 289322/1999, however, another trimming of something other than the AC characteristics is not considered but the trimming of the AC characteristics such as setup/hold characteristic and clock access has been described.
An object of the present invention is to provide a technique enabling estimation in another setting by adjustment, after adjustment using a fuse.
Another object of the invention is to provide a technique enabling adjustment after sealing a semiconductor chip into a package.
The above and the other objects and new features will be apparent from the following description of the invention and the accompanying drawings.